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Applications : Cadence Allegro and OrCAD 17.20.000-2016 HF030 | 1.7 Gb
 
Cadence Allegro and OrCAD 17.20.000-2016 HF030 | 1.7 Gb

Cadence Allegro and OrCAD 17.20.000-2016 HF030 | 1.7 Gb
Cadence Design Systems, Inc. has released an update (HF030) to OrCAD Capture, PSpice Designer and PCB Designer 17.20.000-2016. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.







1821774 ADW DBEDITOR MPN is tagged Pending Purge after deletion and lib_dist
1829549 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase DRC marker displayed at the design origin
1690998 ALLEGRO_EDITOR INTERFACES Runtime error when running PDF Publisher
1805203 ALLEGRO_EDITOR INTERFACES Runtime error when exporting smart PDF on a large board with all film layers selected
1811698 ALLEGRO_EDITOR INTERFACES Runtime error while exporting PDF
1823818 ALLEGRO_EDITOR INTERFACES Cannot map some step models
1750654 ALLEGRO_EDITOR MANUFACT Cut marks cannot be generated on cut outline.
1828293 ALLEGRO_EDITOR NC Incorrect status returned for backdrill
1825401 ALLEGRO_EDITOR PADS_IN In PADS library translation, pads_lib_in fails to create Placebound_Top as a shape
1825427 ALLEGRO_EDITOR PADS_IN Symbol drawing files (.dra) created after PADS Library translation are not getting renamed to their decals
1825460 ALLEGRO_EDITOR PADS_IN Pins are moved from their correct locations during PADS Library Translation
1831200 ALLEGRO_EDITOR DescriptionTING Incorrect PDF output for traces
1321314 ALLEGRO_EDITOR SHAPE Force update of dynamic shape generates thermal tie that causes net to short
1647585 ALLEGRO_EDITOR SHAPE Void around holes is not circular but of the shape of the bounding box
1830676 ALLEGRO_EDITOR SHAPE XHatch Shape not voiding properly
1821286 ALLEGRO_EDITOR SKILL Using axlSetParam to set static shape clearance parameter crashes PCB Editor
1804662 ASDA DARK_THEME Dark Theme: Change color of selected cells in Rename signals dialog so user can see they are selected
1817486 ASDA NEW_PROJECT Need to save a project with a new name, 'copyprojectas' does not seem to work
1826023 ASDA NEW_PROJECT SDA requires user to go into project settings window twice to add a library
1830632 ASDA SCRIPTING SDA crashes when you type 'find -types' in the Tcl command window
1798864 ASDA VARIANT_MANAG Retain default part visibility when substituting preferred part for variant
1798865 ASDA VARIANT_MANAG Value attribute of variant is off while printing though on for default and view
1798866 ASDA VARIANT_MANAG Variant Printing: Pin numbers printed though set to off on default part
1831836 ASDA VARIANT_MANAG Cannot delete existing variants in design
1821120 CONCEPT_HDL CORE SIGNAL_MODEL attached to a component is not displayed on the canvas in the Attributes form
1824714 CONCEPT_HDL CORE Display issue: Page border disappears when running the command _movetogrid
1822587 CONCEPT_HDL CREFER CRefer crashes on a hierarchical design using split blocks
1825461 CONSTRAINT_MGR CONCEPT_HDL Uprevving to release 17.2-2016 adds NO_XNET_CONNECTIONS on components having custom models
1825968 CONSTRAINT_MGR DATABASE cmxlGetObjects returns all the aliased nets and the physical net that goes to the netlist
1819622 CONSTRAINT_MGR XNET_DIFFPAIR Discrete with NO_XNET_CONNECTION removed from topology when extracted with Routed Interconnect
1829762 ECW PROJECT_MANAG Pulse log in: Multiple processes triggered, generating many zip file packets and corrupting many of the packets
1810296 F2B BOM BOM includes status column, nothing should ever be forced on a users BOM output
1824593 F2B PACKAGERXL PXL crashes and removes the pxl.log file from the Packaged directory
1832005 F2B PACKAGERXL Message stating 'PXL has stopped working' when packaging design
1822912 RF_PCB AUTO_PLACE rf_autoplace fails for RF component containing variable
1803731 SIP_LAYOUT DXF_IF DXF export from 'Component Geometry/Pin_Number' subclass not working in release 17.2-2016
1825478 SIP_LAYOUT SHAPE When running the Shape Islands report it is listing all the Fillets as Islands

About Allegro and OrCAD 17.2-2016. The OrCAD 17.2-2016 release introduced new capabilities for OrCAD Capture, PSpice Designer, and PCB Designer 17.2-2016 that address challenges with flex and rigid-flex design as well as mixed-signal simulation complexities in IoT, wearables, and wireless mobile devices. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.
- OrCAD Flex and Rigid-Flex Technologies
To enable a faster and more efficient flex and rigid-flex design creation critical to IoT, wearables and wireless devices, the OrCAD 17.2-2016 portfolio enables several new capabilities for flex and rigid flex design to minimize design iterations. Key flex and rigid flex features include: Stack-up by zone for flex and rigid-flex designs, Inter-layer checks for rigid-flex designs, Contour and arc-aware routing.
- New Cross-Section Editor
In the OrCAD PCB Designer 17.2-2016 release, the Cross-Section Editor has been redesigned to leverage the underlying spreadsheet technology found in the Constraint Manager. It offers a one-stop shop for features that require the cross section for their setup, such as dynamic unused pad suppression and embedded component design. The Cross-Section Editor has been enhanced to support multiple stackups for rigid-flex design, each capable of supporting conductor and non-conductor layers such as Soldermask and Coverlay.
- New Padstack Editor
A new Padstack Editor has been introduced in OrCAD PCB Editor 17.2-2016 to ease padstack creation through a new modern user interface. In addition to supporting new pad geometries, drill types, additional attributes, and additional mask layers ability to define keep-outs within the padstack with complex geometries for all objects, the new capabilities allow PCB librarians to help PCB designers streamline the design process for complex padstacks, and also the commonly used padstacks.
- OrCAD PCB Designer 17.2-2016 Features
The OrCAD PCB Designer 17.2-2016 release also include new features or enhancements targeted towards improving PCB editors' productivity and ease-of-use. Other new features include: Via2via Line Fattening (HDI), Display Segments Over Voids, Layer Set Based Routing, Diff Pair Routing and DRC, Full Xnet Support, Gloss Commands, Contour Routing, and many more.
- OrCAD Capture Design Difference Viewer
The Graphical Design Difference Viewer is a powerful, real-time, design difference, visual review utility in OrCAD Capture with the ability to perform logical as well as graphical comparisons on a page-by-page basis. The Graphical Design Difference Viewer generates an interactive single-report HTML file that is platform and tool independent, a unique viewing feature to identify the differences leading to changes in circuit behavior as well as differences based on individual object level, thereby helping address the specialized needs of the users.
- Advanced Annotation
With the newly introduced Advanced Annotation feature supported by OrCAD Capture, users can assign reference ranges hierarchically by automatically assigning values and perform annotation on the whole design, on hierarchy block at any level, page and property block, giving them complete control over their component annotation process in the design cycle.
- PSpice Virtual Prototyping
The new virtual prototyping functionality introduced in PSpice helps electrical engineers overcome design challenges by automating the code generation for multi-level abstraction models written in C/C++ and SystemC. This functionality assists them in generating code requiring limited coding capabilities by design engineers and thereby making the process of virtual prototyping extremely convenient and easy.

Note: The ADW product line, individual ADW products, and product family names have been rebranded in release 17.2-2016. The Allegro Design Workbench (ADW) is now referred to as Allegro Engineering Data Management (EDM). For the full list of new and improved features, and fixed bugs please refer to the release notes located

About Hot-Fix. A Hot-Fix enables a customer to receive fixes for urgent problems, without having to wait for the next service pack. Unlike Service Packs (SP), which are scheduled, periodic releases, Hot-Fix releases are not periodically scheduled. Simply requesting a Hot-Fix does not automatically guarantee that the customer will receive it: all Hot-Fix requests first must be approved and accepted by Cadence prior to delivery. Furthermore, a Hot-Fix may contain fixes related to problems reported earlier by different customers. All the files included in the Hot-Fix will nevertheless be installed.

About Cadence. Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.

Product: Cadence Allegro and OrCAD (Including EDM)
Version: 17.20.000-2016 HF030
Supported Architectures: x64
Website Home Page :

Language: english
System Requirements: PC
Supported Operating Systems: Windows 7even or newer / 2008 Server R2 / 2012 Server
System Requirements: Cadence Allegro and OrCAD (Including EDM) version 17.20.000-2016 and above
Size: 1.7 Gb


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