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Applications : Cadence Allegro and OrCAD 16.60.100 - 17.20.026 Hotfix
Cadence Allegro and OrCAD 16.60.100 - 17.20.026 Hotfix

Cadence Allegro and OrCAD 16.60.100 - 17.20.026 Hotfix
OS: Windows 64bit | Language: English | Size: 3.5 GB

To thrive in a competitive market, you need to have differentiated design to deliver better product quality and bring highly innovative products to market more quickly than competitors. OrCAD® provides you production proven, scalable and robust PCB solution with broad ecosystem support to help you meet your product creation goal.

Complete Design Environment
OrCAD PCB design solutions provide a complete set of tools to help you achieve the results you need. From the initial schematic to the final artwork, the platform delivers a complete, integrated workflow.

Comprehensive Circuit and Signal Analysis
The OrCAD environment offers proven analysis tools for signal integrity, analog and mixed signal, EMI analysis, and much more. All of these tools are seamlessly integrated so there are no translation errors.

Customizable to Meet Your Needs
OrCAD tools have a fully open architecture platform. This means you can add unique functionality that is integrated into the program in the form of apps, or you can also build capability and flows yourself.

What's new

Fixed CCRs: SPB 17.2 HF026
CCRID Product ProductLevel2 Title

1765398 ADW DATAEXCHANGE Duplicate MPNs are created when updating MPN classification properties with data exchange
1780147 ADW DBEDITOR 'Associate Footprint from Tree' does not log the information
1790134 ALLEGRO_EDITOR DATABASE Correct spelling in Layer Function definition
1792345 ALLEGRO_EDITOR DATABASE Pastemask is added to bottom layer on backdrilled pins
1792930 ALLEGRO_EDITOR DATABASE Uprev required for all libraries and padstacks to use release 16.6 DRA in release 17.2-2016
1781203 ALLEGRO_EDITOR DFA DFA Spreadsheet Editor not starting from Windows Start menu
1797422 ALLEGRO_EDITOR DFA DFA Spreadsheet Editor not starting from Windows Start menu
1770694 ALLEGRO_EDITOR INTERFACES Incremental IDX does not place unplaced components
1776791 ALLEGRO_EDITOR INTERFACES STEP file not displayed in PCB Editor for mapping
1783515 ALLEGRO_EDITOR INTERFACES PCB Editor reading step model incorrectly
1781485 ALLEGRO_EDITOR MANUFACT Setting ipc2581attrpath results in error 'E- ipc2581attrpath: Variable not defined'
1772713 ALLEGRO_EDITOR MULTI_USER Allegro Symphony Server rejects group moves
1789853 ALLEGRO_EDITOR MULTI_USER Symphony Server rejects updates and hangs frequently
1725591 ALLEGRO_EDITOR OTHER File - Export PDF crashes on the design attached
1736324 ALLEGRO_EDITOR OTHER Export - PDF fails to export PDF
1794071 ALLEGRO_EDITOR PLACEMENT The placement of component is very slow and takes around 3 to 5 minutes per component.
1496199 ALLEGRO_EDITOR SHAPE Overlapping route keepouts result in a broken shape.
1760146 ALLEGRO_EDITOR SHAPE Void offset in Artwork but not in board for a particular instance only
1770372 ALLEGRO_EDITOR SHAPE Overlapping shapes merged in artwork shifts void causing a manufacturing short
1793419 ALLEGRO_EDITOR SHAPE Unexpected shape void in artwork in release 16.6
1796666 ALLEGRO_EDITOR SHAPE DRCs for out-of-date shape while placing single via
1786386 APD EXPORT_DATA Exported dra and pad files do not have right stackup
1765673 APD SHAPE Shape in Cu1 and Cu3 cannot void correctly
1782418 APD SHAPE Artwork is showing unnecessary horizontal lines
1778366 CONCEPT_HDL CHECKPLUS CheckPlus not printing logic design name
1723855 CONCEPT_HDL CORE Cannot use Rename Signal for unnamed wire segment if the wire has a branch to the same instance
1755174 CONCEPT_HDL CORE Unable to create XNETs on the read-only blocks
1765533 CONCEPT_HDL CORE Strokes are slow to respond in release 17.2-2016
1780253 CONCEPT_HDL CORE In Windows mode, with copy command still active and symbol on cursor, DE-HDL stops responding on pressing Delete key
1785069 CONCEPT_HDL CORE Warning box for SPCOCN-2251 needs to be resized and the text formatted correctly
1786030 CONCEPT_HDL CORE Packager fails in release 16.6 but runs successfully in release 17.2-2016
1788077 CONCEPT_HDL CORE Creating new window (new tab) in DE-HDL resets view of original window
1788591 CONCEPT_HDL CORE Wrong pin number displayed after running packager
1776774 CONCEPT_HDL CREFER CRefer crashes without error entry in log file
1328320 CONCEPT_HDL PDF Cannot select/search sig_name in published PDF
1787409 CONCEPT_HDL PDF Minus character at the end of netname causes unexpected string concatenation during PDF Publish
1758122 CONSTRAINT_MGR ANALYSIS Extracted topology for a differential pair is missing a pin-to-pin connection in the top file
1786161 CONSTRAINT_MGR CONCEPT_HDL Random crashes in release 17.2-2016 while working on the schematic editor along with Constraint Manager
1788877 CONSTRAINT_MGR DATABASE Constraint Manager API cmxlImportFile looks for sub-string during replace mode and not explicit names
1800263 CONSTRAINT_MGR OTHER DE-HDL and CM crash when deleting regions
1792000 CONSTRAINT_MGR UI_FORMS Data type of constraint not shown in GUI
1744828 FSP CAPTURE_SCHEM Button appears during 'Generate OrCAD Schematics'
1747568 ORBITIO OTHER Import of .oio file in SiP Layout takes a long time
1765229 PSPICE AA_FLOW Not able to run PSpice MC after setting Assign Tolerance
1770174 PSPICE MISC Issues with DMI Template Code Generator

System Requirements: PC
Supported Operating Systems: Windows XP / Vista / Seven
System Requirements: Cadence SPB OrCAD OrCAD 16.6 - 17.20


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