The system of digital simulation projects based on VHDL, Verilog and "mixed" descriptions of built-in performance analysis, indicating "active" code (code coverage), the comparator time diagrams and visualizer Enhanced Dataflow Window. Main features: high speed simulation for RTL and Gate projects; single simulator kernel and optimized architecture Native Compiled; interactive debugging and analysis module Debug Detective; integrated analysis of Code Coverage; optimization speed simulation using Performance Analyzer Performance Analyzer; exhaustive tracing signals Signal Spy; debugger for C, C and interfaces support Tcl / Tk; support for OS Unix / Windows / Linux.